Computer technology has advanced to a current stage characterized by systems in which each of their building blocks (e.g., the memory, the processor and interfaces to peripherals) are not only represented by a variety of different types, but also in the plurality and with a wide selection of admixtures. Thus, in the same system, one or more processors may coordinate through interfaces with a number of memories, quick to respond to processor requests for data, usually because of incorporation in a common mainframe, and some relatively slow to respond, perhaps because of the necessity to locate remotely; for the latter, connection to the processor unit by lengths of cable introduces a delay inherent in such cabling.
Thus, for the sake of simplicity, consider a system in which a processor, which includes a fast-access integral memory, is operatively connected also (through an interface and cabling) with a slow-access memory. Presume that a memory access transaction involves two phases: a request phase followed by a response phase. During the former, the processor issues an access request signal, an address comprising both a memory unit designation and a bit or word address identifying a location within the selected memory and command signals representing the type of operation desired. During the subsequent response phase, the selected memory unit returns a status (i.e., "busy"or" not busy") signal and signals representing the information content of the addressed location; during this phase, a memory unit remains busy until the information content of the addressed location arrives at the processor. The transition from busy to not busy indicates that the sought information is at the processor input and ready for its use. Such a memory access operation is quite conventional in computer systems, and although its details vary among systems, a generally common characteristic is that transmissions are controlled by the clock pulse signal ("strobe") of the processor.
Assume further that, regardless of which memory is addressed, it is immediately available to service the request, and accordingly, sets up its output register with the sought information. If the processor is arranged to strobe the registers with its clock pulse next following its access request signal, a standard made possible in view of the high speed of the fast memory, the delay because of remoteness of the slow memory will preclude presentation of information to the processor in synchronism with its requests. It is apparent that some provision must be made in strobe sequentially-needed data residing in memories characterized by different access times such that the input stream appears to the processor as though there were but one memory or as though both memories operated identically with regard to access of their content.